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HT1647
4-Level Gray Scale 6416 LCD Controller for I/O mC
Features
* * * * * * * * * * * * *
Operating voltage: 2.7V~5.2V Built-in 32kHz RC oscillator External 32.768kHz crystal oscillator or 32kHz frequency source input Standby current < 1mA at 3V, < 2mA at 5V Internal resistor type: 1/5 bias or 1/4 bias, 1/16 duty Two selectable LCD frame frequencies: 89Hz or 170Hz Max. 6416 patterns, 64 segments and 16 commons Built-in bit-map display RAM: 2048 bits (=64162 bits) Built-in internal resistor type bias generator Six-wire interface (four data wires) Eight kinds of time base/WDT selection Time base or WDT overflow output R/W address auto increment
* * * * * * * * * * *
Built-in buzzer driver (2kHz/4kHz) Power down command reduces power consumption Software configuration feature Data mode and Command mode instructions Three data accessing modes Provides VLCD pin to adjust LCD operating voltage Provides three kinds of bias current programming Control of TN-type, STN-type LCDs and ECB-type LCDs Four-level gray scale output for TN-type, STN-type LCDs panel Four-color output for ECB-type LCDs panel Available in 100-pin QFP and in chip form
Applications
* * *
Toys Games Personal digital assistant
* * *
Cellular phone Global positioning system Consumer electronics
General Description
HT1647 is a peripheral device specially designed for I/O type mC used to expand the display capability. The max. display segment of the device are 1024 patterns (64 segments and 16 commons). It also supports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1647 is a memory mapping and multi-function LCD controller. Since the HT1647 can control ECB-type (Electrically Controlled Birefringence) LCDs in addition to current TN-type (Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs, it can support 4-color display as well as 4-level gray scale display. It displays 4-level gray scale output when HT1647 drives TN-type, STN-type LCDs. It displays four color output when HT1647 drives ECB-type. HT1647 uses PWM (Pulse Width Modulation) technique. The software configuration feature of the HT1647 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and the HT1647. The HT164X series have many kinds of products that match various applications.
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HT1647
4-Level Gray Scale LCD Controller Product Line Selection Table
HT164X COM SEG *Under development *HT1642 8 32 *HT1645 8 64 HT1647 16 64
Block Diagram
OSCO OSCI CS RD WR DB0 DB3 VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r & T im e B a s e G e n e r a to r SEG 63 VLCD IR Q C o n tro l & T im in g C ir c u it
D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it CO M 15 SEG0
N o te : C S : C h ip s BZ,BZ:To W R,RD:W D B0~D B3: CO M 0~CO IR Q : T im e
e le c tio n n e o u tp u ts R IT E c lo c k , R E A D c lo c k D a ta b u s M 1 5 , S E G 0 ~ S E G 6 3 : L C D o u tp u ts b a s e o r W D T o v e r flo w o u tp u t
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HT1647
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 63
100 1
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
81 80
CS RD WR DB0 DB1 DB2 DB3 VSS OSCI OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 T4 NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
HT1647 100 Q FP
30 31
51 50
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM COM COM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 10 11 12 13 14 15
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HT1647
Pad Assignment
SEG 41 SEG 40 SEG 39 SEG 38 SEG 37 SEG 36 SEG 35 SEG 34 SEG 33 SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 76 SEG 17
SEG 42 1 2 3 4 5 6 7 8 9 SEG 43 SEG 44 SEG 45 SEG 46 SEG 47 SEG 48 SEG 49 SEG 50 SEG 51 SEG 52 SEG 53 SEG 54 SEG 55 SEG 56 SEG 57 SEG 58 SEG 59 SEG 60 SEG 61 SEG 62 SEG 63 CS RD WR
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
75
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 CO M 15 CO M 14 CO M 13 CO M 12 CO M 11 CO M 10 COM9 COM8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DB0 DB1 DB2 DB3 VSS OSCI OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 T4 COM0 43 COM1 44 COM2 45 COM3 46 COM4 47 COM5 48 COM6 (0 , 0 )
49 COM7
Chip size: 3865 3770 (mm)
2
* The IC substrate should be connected to VSS in the PCB layout artwork.
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HT1647
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X -1774.50 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1779.30 -1690.00 -1690.00 -1690.00 -1430.20 -1294.80 -1149.50 -1013.90 -872.80 -738.30 -600.10 -465.60 Y 1708.30 1409.80 1281.80 1150.00 1022.00 890.20 762.20 630.40 502.40 370.60 242.60 110.80 -17.20 -149.00 -277.00 -408.80 -536.80 -668.60 -796.60 -928.80 -1056.80 -1189.00 -1375.40 -1515.40 -1651.00 -1599.90 -1599.90 -1599.90 -1599.90 -1600.00 -1600.00 -1600.00 -1600.00 Pad No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 X -331.40 -194.50 -48.00 87.40 235.20 383.40 530.40 678.60 875.00 1003.00 1134.80 1262.80 1394.60 1522.60 1654.40 1782.40 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 Y -1600.00 -1558.30 -1600.00 -1600.00 -1600.00 -1600.00 -1600.00 -1600.00 -1712.30 -1712.30 -1712.30 -1712.30 -1712.30 -1712.30 -1712.30 -1712.30 -1411.10 -1283.10 -1151.30 -1023.30 -891.50 -763.50 -631.70 -503.70 -371.90 -243.90 -112.10 15.90 147.70 275.70 407.50 535.50 667.30 Pad No. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 X 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1775.70 1471.10 1343.10 1211.30 1083.30 951.50 823.50 691.70 563.70 431.90 303.90 172.10 44.10 -87.70 -215.70 -347.50 -475.50 -607.30 -735.30 -867.10 -995.10 -1126.90 -1254.90 -1386.70 -1514.70 -1646.50 Unit: mm Y 795.30 927.10 1055.10 1186.90 1314.90 1446.70 1574.70 1706.50 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30 1708.30
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HT1647
Pad Description
Pad No. Pad Name I/O Description Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1647 are disabled. The serial interface circuit is also reset. But if the CS is at a logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1647 are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT1647 are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1647 on the rising edge of the WR signal. Negative power supply for logic circuit, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. Positive power supply for logic circuit Power supply for LCD driver circuit Time base or Watchdog Timer overflow flag, NMOS open drain output. 2kHz or 4kHz frequency output pair (tristate output buffer) Not connected LCD common outputs LCD segment outputs
23
CS
I
24
RD
I
25 26~29 30 31 32 33 34 35 36, 37 38~41 42~57 58~99, 1~22
WR DB0~DB3 VSS OSCI OSCO VDD VLCD IRQ BZ, BZ T1~T4 COM0~COM15 SEG0~SEG63
I
I/O Parallel data input/output with a pull-high resistor 3/4 I O 3/4 I O O I O O
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage ................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT1647
D.C. Characteristics
Symbol VDD IDD1 IDD2 IDD11 IDD22 ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH Parameter Operating Voltage Operating Current Operating Current Operating Current Operating Current Standby Current Input Low Voltage Input High Voltage BZ, BZ, IRQ Sink Current BZ, BZ Source Current DB0~DB3 Sink Current DB0~DB3 Source Current LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current Pull-high Resistor Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD OFF On-chip RC oscillator No load/LCD OFF Crystal oscillator No load Power down mode DB0~DB3, WR, CS, RD DB0~DB3, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DB0~DB3, WR, CS, RD Ta=25C Min. Typ. Max. Unit 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.4 4.0 1.2 3 -0.9 -2 1.2 3 -0.9 -2 50 100 -25 -50 30 60 -20 -35 150 60 3/4 150 250 135 200 15 50 2 3 3/4 3/4 3/4 3/4 3/4 3/4 2.5 6 -1.8 -4 2.5 6 -1.8 -4 100 200 -50 -100 60 120 -40 -70 250 125 5.2 250 370 200 300 30 70 10 10 1 2 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 350 180 V mA mA
mA
mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW kW
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HT1647
A.C. Characteristics
Symbol fSYS1 fSYS2 fSYS3 fLCD1 fLCD2 fLCD3 tCOM fCLK1 fCLK2 tCS Parameter System Clock System Clock System Clock LCD Frame Frequency LCD Frame Frequency LCD Frame Frequency LCD Common Period 4-Bit Data Clock (WR Pin) 4-Bit Data Clock (RD Pin) 4-Bit Interface Reset Pulse Width (Figure 3) WR, RD Input Pulse Width (Figure 1) Test Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3V 5V 3V 5V 3/4 3V 5V Conditions On-chip RC oscillator Crystal oscillator External clock source On-chip RC oscillator Crystal oscillator External clock source n: Number of COM Duty cycle 50% Duty cycle 50% CS Write mode Read mode Write mode Read mode 3/4 3/4 3/4 3/4 3/4 Min. 22 24 3/4 3/4 3/4 3/4 44 48 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.34 6.67 1.67 3.34 3/4 3/4 3/4 3/4 3/4 Typ. 32 32 32.768 32.768 32 32 64 64 64 64 64 64 n/fLCD 3/4 3/4 3/4 3/4 250 3/4 3/4 120 120 120 100 100 Ta=25C Max. Unit 40 40 3/4 3/4 3/4 3/4 80 80 3/4 3/4 3/4 3/4 3/4 150 300 75 150 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz sec kHz kHz kHz kHz ns ms ms ns ns ns ns ns
tCLK
tr, tf tsu th tsu1 th1
Rise/Fall Time Serial Data 3V Clock Width (Figure 1) 5V Setup Time for DB to WR, RD Clock Width (Figure 2) Hold Time for DB to WR, RD Clock Width (Figure 2) 3V 5V 3V 5V
Setup Time for CS to WR, RD 3V Clock Width (Figure 3) 5V Hold Time for CS to WR, RD Clock Width (Figure 3) 3V 5V
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HT1647
V A L ID DATA V th
u
tf
tr
V
DB
DD
50% ts
DD
GND
W R,RD C lo c k
90% 50% 10%
tC
LK
tC
GND
LK
W R,RD C lo c k
50%
GND
Figure 1
tC
S
Figure 2
V
DD
CS
50% ts
u1
th
1
GND V
DD
W R,RD C lo c k
50% F IR S T C lo c k LAST C lo c k
GND
Figure 3
Functional Description
System oscillator The HT1647 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (32kHz), a crystal oscillator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well.
OSCI OSCO C r y s ta l O s c illa to r 32768H z E x te r n a l C lo c k S o u r c e 32kH z O n - c h ip R C O s c illa to r 32kH z
The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 32kHz clock source operation. At the initial system power on, the HT1647 is at the SYS DIS state.
S y s te m C lo c k
System oscillator configuration
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HT1647
Display memory - RAM structure The static display RAM is organized into 5124 bits and stores the display data. Two bits of RAM map to Lads one pixel and decide whether 4-level gray scale or 4-color display
CO M 15 SEG0 SEG1 SEG2 SEG3 CO M 14 7 15 8 16 24 A d d r e s s 9 B its (A 8 , A 7 , ...., A 0 ) 23 31
concurrently. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.
COM1 COM0 0
SEG 63 D3 D2 D1 D0
511 Addr D a ta D a ta 4 B its (D 3 , D 2 , D 1 , D 0 ) D3 D2 D1 D0
504 Addr D a ta
: T w o b it s o f R A M m a p t o L C D 's o n e p ix e l a n d d e c id e 4 - le v e l g r a y s c a le o r 4 - c o lo r d is p la y c o n c u r r e n tly .
Display memory - RAM structure Gray scale level decision HT1647 uses PWM technique to provide 4-level gray scale display. Two bits of RAM data code ((D3, D2) or (D1, D0)) decide one pixel level of LCDs, level 1~level 4 dividedly. Every level must be defined as one kind of gray scale by PWM data (namely B4~B0) previously. RAM data code Choice Gray Scale (D3, D2) or (D1, D0) Level (1, 1) (1, 0) (0, 1) (0, 0) Level 1 Level 2 Level 3 Level 4 Frame frequency HT1647 provides two kinds frame frequency option by command code, 89Hz and 170Hz respectively. FRAME 89Hz provides 89Hz frame frequency and active segment signal width can be divided into 24 sections concurrently. FRAME 170Hz provides 170Hz frame frequency and active segment signal width can be divided into 13 sections concurrently. The 24 sections display a particularly gray scale more than the 13 sections by PWM data. The default is FRAME 89Hz. Gray scale display If the user choose 89Hz frame frequency, a max. of 24 sections can be programmed to suit a satisfactory gray scale in every level. Similarly, if the user choose 170Hz frame frequency, a max. of 13 sections can be programmed to suit a satis10 April 21, 2000
RAM data defined gray scale level
HT1647
Name FRAME 170Hz FRAME 89Hz Command Code X100-0001-1000-XXXX X100-0001-1101-XXXX Function Select 170Hz frame frequency and active segment signal width can be divided into 13 sections Select 89Hz frame frequency and active segment signal width can be divided into 24 sections
Frame frequency selection command code factory gray scale in every level. HT1647 provides 5-bit PWM data to control the length of the section. In other words, a max. 24 gray scales are generated by 5-bit binary PWM data. At FRAME 89Hz mode, the HT1647 only provides a max. of 24 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When 5 bits binary code value is more than 23, the PWM control circuit uniformly regards 23. To increase PWM data indicates to increase the length of the active segment signal. The varied length of the active segment signal displays varied gray scale in Name GRS LEVEL 1 GRS LEVEL 2 GRS LEVEL 3 GRS LEVEL 4 Command Code TN-type, STN-type LCDs (refer to table 1). Similarly, it displays varied color in ECB-type LCDs. The color display is derived from ECB-type LCD specification. At FRAME 170Hz mode, the HT1647 only provides a max. of 13 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When the 5 bits binary code value is more than 12, the PWM control circuit uniformly regards 12. The user must appoint four kinds of PWM data to four kinds of different gray scale level by commanding PWM data (refer to table 2). Function
X100-001 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 1 X100-010 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 2 X100-011 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 3 X100-100 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 4 Four kinds of gray scale level command code
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HT1647
16 V COM V
LCD
1
2
16
1
2
V1 V2 V3 V4
SS
W V SEG V
LCD
W'
V1 V2 V3 V4
SS
W' V 3 /5 V CO M ~SEG 1 /5 V -1 /5 V -3 /5 V -V
LCD LCD LCD LCD LCD LCD
W
ON
OFF 1 fra m e
ON
N o t e : " W '" R e a l a c t iv e s e g m e n t s ig n a l w id t h ( a d ju s t a b le w id t h b y P W M " W " M a x . a c tiv e s e g m e n t s ig n a l w id th P W M ( O N w id t h ) : W '/ W , 0 < W '/ W < 1 ( r e f e r t o t a b le 1 & t a b e l 2 )
Example of waveform (B type) in 1/5 bias, 1/16 duty cycle drive
d a ta )
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HT1647
Time base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will
T im e B a s e C lo c k S o u r c e /2 5 6 V CLR T im e r
DD
remain at a logic low level until the CLR WDT or the IRQ DIS command is issued. If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed.
T IM E R
E N /D IS
IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT /4
CLR W DT
Time base and WDT configurations Buzzer tone output A simple tone generator is implemented in the HT1647. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable and turn on tone output. The TONE Name TONE OFF TONE 4K TONE 2K Command Code X100-0000-1000-XXXX X100-0001-0000-XXXX X100-0001-0001-XXXX Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. Function
Buzzer tone output command code Command format The HT1647 can be configured by software setting. There are two mode commands to configure the HT1647 resource and to transfer the LCD display data. The configuration mode of the HT1647 is called command mode, and its command mode ID is 100. The command mode consists of a system configuration command, a system frequency selection command, an LCD configuration command, a tone frequency selection command, a bias current selection command, a gray scale level selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations.
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HT1647
The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100 Bias generator The HT1647 bias voltage belong to internal resistor type. It provides two kinds of bias option named 1/5 bias and 1/4 bias respectively. It is recommeaded to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs. It also provides three kinds of bias current option by programming to suitably drive LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during on condition when the LCD is normally displayed. The following are the reference value table. Middle bias current 100mA 125mA
VDD * VLCD R V1 R V2 R V3 R R V4 R R VSS 1 /4 b ia s VSS 1 /5 b ia s V4 *V
LCD
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will also be reset. The CS pin returns to 0, so a new operation mode ID should be issued first. VLCD 4V 4V Bias 1/5 1/4
VDD VR
Large bias current 300mA 375mA
Small bias current 40mA 50mA
* VLCD R V1 V2 R V3 R *V
VR
LCD
* T h e v o lta g e a p p lie d to V L C D p in m u s t b e lo w e r th a n V D D * A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W
20%
Internal resistor type bias generator configurations
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April 21, 2000
HT1647
Interfacing Only six lines are required to interface with the HT1647. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1647. If the CS pin is set to 1, the data and command issued between the host controller and the HT1647 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1647. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all clocked into the HT1647 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1647. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1647.
Relationship table between PWM data and gray scale
V a lu e 0 1 2 3 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 4 5 b its P W M B4 B3 B2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 d a ta B1 B0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 (O N PW M w id th ) G r a y S c a le 0 (0 /2 3 ) 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 1 (2 3 /2 3 ) 1 (2 4 /2 3 ) 1 1 1 1 1 1 1 1 1 1 2 2 2
Frame 89Hz mode (table 1)
V a lu e 0 1 2 3 4 5 6 8 9 10 11 12 13 7 5 b its P W M B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 d a ta B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (O N PW M w id 0 (0 /1 1 /1 2 2 /1 2 3 /1 2 4 /1 2 5 /1 2 6 /1 2 7 /1 2 8 /1 2 9 /1 2 0 /1 2 1 /1 2 (1 2 /1 (1 3 /1 th ) 2) G r a y S c a le
1 1 1 1
2) 2)
31
1 1
1
1
1
1 (3 1 /1 2 )
N o te : T h e g ra y The LCD
v a r ie d s c a le c o lo r 's s p e
PW in T d is p c ific
M d a ta d is p la y v a r ie d N -ty p e , S T N -ty p e L C D s . la y d e r iv e s fr o m E C B - ty p e a tio n .
31
1 1
1
1
1
1 (3 1 /2 3 )
15
April 21, 2000
D a ta (M A + 1 5 ) D a ta (M A + 1 4 ) D a ta (M A + 1 3 ) D a ta (M A + 1 2 ) D a ta (M A + 1 1 ) D a ta (M A + 1 0 ) ( S u c c e s s iv e a d d r e s s r e a d in g ) D a ta (M A + 9 ) D a ta (M A + 8 ) D a ta (M A + 7 ) D a ta (M A + 6 ) D a ta (M A + 5 ) D a ta (M A + 4 ) D a ta (M A + 3 ) D a ta (M A + 2 ) D a ta (M A + 1 ) D a ta (M A ) M e m o ry A d d re s s (M A )
D3
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D2
D3
D1
D1
D2
D3
D1
D2
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
A5
A7
A6
A4
C o m m a n d ID 0
code
A8
READ mode (command ID code : 1 1 0)
1
1
Timing Diagrams
D a ta (M A ) D3 D1 D2 D0 M e m o ry A3 A2 A1 A0 A d d re s s (M A ) A7 A6 A5 A4 C o m m a n d ID A8 1 1 0 code
WR
DB3
DB2
DB1
DB0
CS
RD
( S in g le a d d r e s s r e a d in g )
16
A3
A2
A1
A0
April 21, 2000
HT1647
D3
D3
D2
D1
D3
D2
D1
D2
D1
D0
D0
D0
D a ta (M A + 1 5 ) D a ta (M A + 1 4 ) D a ta (M A + 1 3 ) D a ta (M A + 1 2 ) D a ta (M A + 1 1 ) D a ta (M A + 1 0 ) ( S u c c e s s iv e a d d r e s s w r itin g ) D a ta (M A + 9 ) D a ta (M A + 8 ) D a ta (M A + 7 ) D a ta (M A + 6 ) D a ta (M A + 5 ) D a ta (M A + 4 ) D a ta (M A + 3 ) D a ta (M A + 2 ) D a ta (M A + 1 ) D a ta (M A ) M e m o ry A d d re s s (M A ) C o m m a n d ID c o d e
D3
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D3
D2
D1
D2
D1
D3
D2
D1
D3
D2
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
A3
A1
A7
A2
A6
A5
A8
WRITE mode (command ID code : 1 0 1)
1
0
1
A4
A0
D3
D2
D a ta (M A ) D1 D0 M e m o ry A3 A2 A1 A0 A4 A d d re s s (M A ) A7 A6 A5 C o m m a n d ID c o d e A8 1 0 1
WR
DB3
DB2
DB1
DB0
CS
RD
( S in g le a d d r e s s w r itin g )
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HT1647
D3
D3
D2
D1
D2
D1
D0
D0
HT1647
READ-MODIFY-WRITE mode (command ID code : 1 0 1)
CS
WR
RD
DB3
A8
A7
A3
D3
D3
A8
A7
A3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
DB2
1
A6
A2
D2
D2
1
A6
A2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
DB1
0
A5
A1
D1
D1
0
A5
A1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
DB0
1 C o m m a n d ID code
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0 D a ta (M A )
1 C o m m a n d ID code
A4 A d d re s s (M A )
A0 M e m o ry
D0 D a ta (M A )
D0 D a ta (M A )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 1 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 2 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 3 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 4 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 5 )
D0 D a ta (M A + 6 )
D0 D a ta (M A + 6 )
( S in g le a d d r e s s a c c e s s in g )
( S u c c e s s iv e a d d r e s s a c c e s s in g )
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April 21, 2000
HT1647
Command mode (command ID code : 1 0 0)
CS
WR
RD
DB3
X
C8
C4
C0 X
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
C8
C4
C0
DB2
1
C7
C3
X
1
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3
X
C7
C3 X
DB1
0
C6
C2
X
0
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2
X
C6
C2 X
DB0
0 C o m m a n d ID code
C5
C1 Com m and
X
0 C o m m a n d ID code
C5
C1 Com m and 1
X
C5
C1 Com m and 2
X
C5
C1 Com m and 3
X
C5
C1 Com m and 4
X
C5
C1 Com m and 5
X
C5
C1 X Com m and 6
( S in g le c o m m a n d )
( S u c c e s s iv e c o m m a n d )
Note: X stands for dont care
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April 21, 2000
HT1647
Application Circuits
Host controller with an HT1647 display system
*
mC
*R
CS RD WR D B0~D B3 VDD *V R
HT1647
VLCD BZ P ie z o BZ
IR Q OSCI C lo c k O u t E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C * 1 /5 B ia s ( o r 1 /4 B ia s ) , 1 /1 6 D u ty OSCO C O M 0 ~ C O M 15 SEG 0~SEG 63
LCD
C ry s ta l 32768H z
Panel
*Note:
The connection of IRQ and RD pin can be selected depending on the mC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW 20%. It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fitm ECB-type LCDs. Adjust R (external pull high resistance) to fit users time base clock.
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April 21, 2000
HT1647
Instruction Set Summary
Name READ WRITE READMODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON WDT DIS WDT EN CLR TIMER CLR WDT TONE 4K TONE 2K IRQ DIS IRQ EN RC 32K EXT (XTAL) LARGE BIAS MIDDLE BIAS Command Code D/C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn Off both system oscillator and LCD bias generator Turn On system oscillator Turn Off LCD display Turn On LCD display Disable time base output Enable time base output Enable WDT time-out flag output Turn Off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage Turn on tone output, tone frequency output: 4kHz Turn on tone output, tone frequency output: 2kHz Disable IRQ output Enable IRQ output System clock source, on-chip RC oscillator System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Large bias current option Middle bias current option Yes Yes Yes Yes Yes Disable WDT time-out flag output Yes Yes Yes Def. A8110-A7A6A5A4A3A2A1A0D3D2D1D0 D A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D X100-0000-0000-XXXX X100-0000-0001-XXXX X100-0000-0010-XXXX X100-0000-0011-XXXX X100-0000-0101-XXXX X100-0000-0111-XXXX C C C C C C C C C C C C C C C C C C C
TIMER DIS X100-0000-0100-XXXX TIMER EN X100-0000-0110-XXXX TONE OFF X100-0000-1000-XXXX X100-0000-1101-XXXX X100-0000-1111-XXXX X100-0001-0000-XXXX X100-0001-0001-XXXX X100-0001-0010-XXXX X100-0001-0011-XXXX X100-0001-0100-XXXX X100-0001-0101-XXXX X100-0001-0110-XXXX X100-0001-0111-XXXX
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April 21, 2000
HT1647
Name SMALL BIAS BIAS 1/5 BIAS 1/4 FRAME 170Hz FRAME 89Hz GRS LEVEL1 GRS LEVEL2 GRS LEVEL3 GRS LEVEL4 F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Command Code X100-0001-1000-XXXX X100-0001-1001-XXXX X100-0001-1010-XXXX X100-0001-1100-XXXX D/C C C C C Function Small bias current option LCD 1/5 bias option LCD 1/4 bias option Select 170Hz frame frequency and active segment signal width can be divided 13 sections Select 89Hz frame frequency and active segment signal width can be divided 24 sections Set PWM data in gray scale level 1 Set PWM data in gray scale level 2 Set PWM data in gray scale level 3 Set PWM data in gray scale level 4 Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2 s Time base clock output: 16Hz The WDT time-out flag after: 1/4 s Time base clock output: 32Hz The WDT time-out flag after: 1/8 s Time base clock output: 64Hz The WDT time-out flag after: 1/16 s Time base clock output: 128Hz Yes The WDT time-out flag after: 1/32 s Test mode, user dont use. Normal mode Yes Yes Yes Def.
X100-0001-1101-XXXX X100-001 B4-B3 B2 B1 B0-XXXX X100-010 B4-B3 B2 B1 B0-XXXX X100-011 B4-B3 B2 B1 B0-XXXX X100-100 B4-B3 B2 B1 B0-XXXX X100-1010-0000-XXXX X100-1010-0001-XXXX X100-1010-0010-XXXX X100-1010-0011-XXXX X100-1010-0100-XXXX X100-1010-0101-XXXX X100-1010-0110-XXXX X100-1010-0111-XXXX X100-1111-1111-XXXX X100-1111-1110-XXXX
C C C C C C C C C C C C C C C
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April 21, 2000
HT1647
Note: X stands for dont care A8~A0 : RAM address D3~D0 : RAM data B4~B0 : PWM data D/C : Data/Command mode Def. : Power-on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1647 after power-on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1647.
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April 21, 2000
HT1647
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright a 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
24
April 21, 2000

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